This invention relates to a pulse train producing apparatus which generates a plurality of pulse trains of phases different from one another and supplies such pulse trains to various parts of a processing apparatus such as an information processor.
A pulse having a basic signal waveform or rectangular waveform as shown in FIG. 1 is generally used as such a clock pulse. Referring to FIG. 1, the rising and falling waveform portions of the pulse are designated by LE (leading edge) and TE (trailing edge) respectively, and the peak value of the waveform portion between the leading and trailing edges LE and TE represents the amplitude Vp of the pulse. The duty ratio D is an important parameter indicative of the quantity of effective energy of a pulse signal as shown in FIG. 1. This duty ratio D is given by EQU D=(t.sub.w /T).times.100(%) (1)
where t.sub.w is the pulse width, and T is the pulse interval.
However, an actual rectangular pulse is not exactly rectangular in shape and includes sloped skirt portions in both the leading and trailing edges, as shown in FIG. 2. In the pulse waveform shown in FIG. 2, the period of time required for the pulse waveform to rise up to 90% of the amplitude from the zero level is called the rise time t.sub.r, the period of time required for the pulse waveform to fall down to 10% of the amplitude from the 100% level is called the fall time t.sub.f, and the period of time between 50% of the amplitude on the leading edge and 50% of the amplitude on the trailing edge is called the pulse width t.sub.w.
Further, a sag SG, a overshoot OS, a ringing RG, etc. may sometimes occur on a rectangular pulse as shown in (a) and (b) of FIG. 3. The sag SG occurs when the low-frequency characteristic of the circuit is not good or when a capacitive coupling, a pulse transformer or the like is present in the circuit. The ringing RG is caused by an inductance component present in the circuit and frequently affects undesirably against the process.
In an information processor requiring highspeed information processing, referred to merely as processor hereinafter, a plurality of clock pulse groups or trains different in phase from one another are generally used to proceed processing of the processor as changing the signalling states of internal registers, flip-flop and the like. Clock pulses supplied to such a processor are required to be quite accurate in their phase and pulse width. Therefore, with the increase in the processing speed of such a processor, the phase and pulse width of the clock pulses must be more strictly controlled.
In a processor designed to operate at a high speed, an oscillator, for example, a crystal oscillator capable of oscillation with least fluctuation in its oscillation frequency is used as a clock pulse generator, and the clock pulses generated from the crystal oscillator are then finely adjusted in their phase and pulse width before being distributed to various logic operation parts of the processor.
FIG. 4 is a block diagram of a prior art clock pulse producing apparatus, FIG. 5 is a time chart of the clock pulses produced by the apparatus shown in FIG. 4, and FIG. 6 shows the structure of the pulse width adjusting circuit in the apparatus shown in FIG. 4.
In the apparatus shown in FIG. 4, the oscillation output from a crystal oscillator 1 is applied to a pulse shaping unit 2 to be shaped into rectangular clock pulses so that clock pulses having phases determined depending on the function of a processor can be supplied to the processor. FIG. 4 shows that four kinds of clock pulse different in phase from one another appear on respective output lines 101 to 104 of the pulse shaping unit 2.
The clock pulses appearing on the output lines 101, 102, 103 and 104 shown in FIG. 4 are designated by a.sub.0, a.sub.1, a.sub.2 and a.sub.3 respectively in FIG. 5. Referring to FIG. 5, one machine cycle T is equally divided into four phases T.sub.0, T.sub.1, T.sub.2 and T.sub.3 to which the clock pulses a.sub.0, a.sub.1, a.sub.2 and a.sub.3 are allotted respectively so that the four kinds of clock pulses turn on at the phases T.sub.0, T.sub.1, T.sub.2 and T.sub.3 respectively. The pulse width of each of these clock pulses a.sub.0 to a.sub.3 is 1/4 T.
Although the clock pulses a.sub.0 to a.sub.3 shown in FIG. 5 have already been roughly or finely adjusted in their phase and pulse width in the pulse shaping unit 2, there is also a pulse shaping unit in which no adjustment is applied to the phase and pulse width.
Returning to FIG. 4, the clock pulses appearing on the output lines 101 to 104 of the pulse shaping unit 2 are applied to a clock distributor unit 3 in which, regardless of whether or not the clock pulses have been adjusted in their phase and pulse width in the pulse shaping unit 2, the clock pulses are finally finely adjusted in their phase and pulse width in a phase adjusting section 31 and a pulse width adjusting section 32 before being distributed to a plurality of logic operation parts of the processor. The operation of the clock distributor unit 3 will be described in more detail by reference to one of the clock pulses, for example, the clock pulse a.sub.0. The clock pulse a.sub.0 appearing on the output line 101 of the pulse shaping unit 2 is applied through an amplifier gate 4 to a phase adjusting circuit 5 in the phase adjusting section 31. After having been adjusted in its phase in the phase adjusting circuit 5 in the phase adjusting section 31, the clock pulse a.sub.0 is applied by way of an output line 108 to an amplifier gate 6 in the pulse width adjusting section 32. The clock pulse a.sub.0 is then applied by way of an output line 105 to a pulse width adjusting circuit 7 in the pulse width adjusting section 32 to be finely adjusted in its pulse width. The clock pulse a.sub.0 having been thus adjusted in both the phase and the pulse width passes through another amplifier gate 8 in the pulse width adjusting section 32 to be applied by way of an output line 107 to source gates 9 and 10 provided for supplying the clock pulse a.sub.0 to the associated logic operation part of the processor.
It is to be added herein that the number of amplifier gates or source gates is not always fixed because it is dependent upon the factors including the electrical characteristics of the transmission circuit system of the processor and the physical distances upto the logic operation parts supplied with the clock pulses.
There are two reasons why the phase and pulse width of the clock pulses must finally be finely adjusted in the clock distributor unit 3. In the first place, the phase and pulse width of the clock pulses being transmitted by way of the output lines 101 to 104 to the clock distributor unit 3 tend to deviate from the settings due to the physical or electrical characteristics of the transmission lines. Secondly, it is impractical to finally finely adjust the phase and pulse width of the individual clock pulses at the respective associated logic operation parts of the processor after they have been supplied from the clock distributor unit 3.
There are various methods of phase adjustment in the phase adjusting circuits 5 in the phase adjusting section 31 shown in FIG. 4. For example, independently adjustable delay lines may be connected in series with the individual clock pulse lines of different phases respectively.
Also, there are various methods of pulse width adjustment in the pulse width adjusting circuits 7 in the pulse width adjusting section 32 shown in FIG. 4. For example, a combination of an AND gate 11, a delay line 12 and an inverter 13 as shown in FIG. 6 may be used.
FIG. 6 shows the structure of one form of the pulse width adjusting circuit 7 which makes fine adjustment of the pulse width to readjust it to the value of 1/4 T when the pulse width shown in FIG. 5 exceeds the value of 1/4 T. Referring to FIG. 6, the clock pulse having been adjusted in its phase is applied by way of the output line 105 to one of the input terminals of the AND gate 11 and also to the delay line 12. After being delayed by a delay time t in the delay line 12, the clock pulse is applied through the inverter 13 to the other input terminal of the AND gate 11 by way of an input line 107. Thus, when the delay time t is set at t=1/4 T, the trailing edge portion of the clock pulse is cut away at the position of 1/4 T from the leading edge which is taken as the reference position, so that the pulse width can be adjusted to be 1/4 T.
When, on the other hand, the circuit system is such that the pulse width will become shorter than 1/4 T in the course of clock pulse transmission to the clock distributor unit 3, the inverter 13 in the circuit shown in FIG. 6 may be eliminated, and the AND gate 11 may be replaced by an OR gate so that the pulse width of the clock pulse applied by way of the line 105 may be extended by the time t. In such a case, the time t of the delay line 12 may be set to compensate for the decrement of the pulse width during clock pulse transmission.
When such a prior art clock distributor unit 3 is incorporated in processors to distribute clock pulses, the phase adjusting circuits 5 and the pulse width adjusting circuits 7 thereof must be regulated at a suitable time of the manufacturing process for each individual processor. Especially, in this case, the regulation of the pulse width adjusting circuits 7 is encountered with problems.
One of the problems is attributable to the fact that the clock pulses applied to the clock distributor unit 3 inevitably fluctuate in width arround its designed setting. Therefore, an adjusting function for increasing the pulse width and an adjusting function for decreasing the pulse width are both required, and, for the realization of these two functions, the circuit structure of the pulse width adjusting circuits 7 shown in FIG. 4 will become extremely complex. It is another problem that the possible difference in accuracy among the respective pulse width adjusting circuits 7 makes it further difficult to precisely control the pulse width.
As one of the measures for solving the above problems, it has been proposed to previously adjust the pulse width in the pulse shaping unit 2 in such a manner that the pulse width tends to normally decrease or increase relative to the designed setting within a limited range. In such a case too, delay time values t peculiar to individual processors must be separately determined, and a lot of man-hours are required for the purpose of regulation of the pulse width adjusting circuits 7.